RTL to tapeout.Silicon design through intelligent automation.
A US based electronic design automation (EDA) and design services company committed to reducing time to market and cost of back end (RTL-to-GDS) SoC and ASIC design.
WHAT WE DO
Automate backend design for predictable tapeouts.
Our automation reduces turnaround time, enables lower-headcount tapeouts, and optimizes PPA. We can license it to help your team, or handle the backend design for you.
Backend Design Services
Backend implementation at every level of engagement, from contracting with your team, to independent tapeout.
Learn more →Flow Automation
Flow setup, methodology review, and node migration planning. We audit your current flow and fix bottlenecks before they cost you a respin.
Learn more →Node Migration
Moving your design to an advanced process node. We handle the infrastructure changes, DRC updates, and timing re-closure so you avoid costly respins.
Learn more →Training
Hands-on workshops in Tcl, Python, and EDA tool flows. Upskill your team to build automated, vendor-agnostic design environments.
Learn more →THE TEAM
The people behind the silicon
Automation-backed execution that ships better silicon with less overhead.
Justin Kernen
CEO
20-year veteran of backend SoC design. Has taped out dozens of chips at three of the world's largest semiconductor companies. Specializes in RTL-to-GDS flow automation and physical design methodology across nodes from 90nm to 3nm.
Matt Mikhailov
CTO
Physical Design and PD CAD Engineer with a background in high-performance computing.
Yuchen Jing
Software Engineer
Experienced Rust developer with a background in high-performance computing, full stack development, DevOps, and security.
Tynan McAuley
SoC RTL Lead
Architect of Domain-Specific Accelerators, with a decade of chip design experience. Expert in RTL design and proficient software developer.
Utkarsh Salvi
DV Engineer
DV Engineer with enthusiasm for automation. Graduated from USC in May 2025.
BLOG
From the blog
Perspectives on EDA flows, backend methodology, automation, and how modern silicon programs get built and delivered.
CAREERS
We're hiring
Senior engineers who want real ownership — on real programs, shipping real silicon.
RISC-V CPU Architect/RTL Lead
Austin, TX · Remote · Full time
$225,000–$300,000 / year
Design Verification Lead
Austin, TX · Remote · Full time
$225,000–$300,000 / year
You'll work on customer execution and internal automation side by side, helping shape how modern VLSI programs get delivered faster and with less waste.
Let’s talk.
Whether you need support from RTL to tapeout, want to evaluate our automation approach, or are trying to deliver silicon more efficiently than a traditional services model allows, we’d love to talk.
Get in touch →