20-year veteran of backend SoC design. Has taped out dozens of chips at three of the world's largest semiconductor companies. Specializes in RTL-to-GDS flow automation and physical design methodology across nodes from 90nm to 3nm.

Physical Design and PD CAD Engineer with a background in high-performance computing.

Experienced Rust developer with a background in high-performance computing, full stack development, DevOps, and security.

Architect of Domain-Specific Accelerators, with a decade of chip design experience. Expert in RTL design and proficient software developer.

DV Engineer with enthusiasm for automation. Graduated from USC in May 2025.