IP Terminology (definitions for VLSI)

There is often confusion in the industry about what exactly these words mean as they are often used interchangeably and can change based on context, perspecitve, or company. This is an attempt to distignuish them and try to create standard definitions.

IP: any intellectual property

• Design: The context or scope of the work or tool. i.e. current_design
• Chip/Die: a design that is manufactured on a single piece of silicon and has its own bumps or passivation (holes) to be packaged
• SoC: system on a chip, a chip that consists of multiple modules and interfaces
• Chiplet: A chip intended to be co-packaged with one or more other chips
• SiP: system in package, a collection of chiplets to be manufactured as a single package.
• Subsystem/Subchip: a design that consists of multiple blocks and may contain its own bumps but cannot be manufactured independently. e.g. pcie
• Module: any level of hierarchy that exists as a module statement in verilog
• Instance: an instance of a module or macro
• Hierarchical instance: an instance that is purely logical and contains other modules, macros, or stdcells. (can be converted to a block or black box)
• MIM: multiply instantiated module, when more than one instance of the same module exists. They must be physically identical.
• Macro: the physical definition of a module or physical only instance, consists of physical IP such as lef/gds. A macro is a black box that cannot be modified by its parent and is typically used multiple times.
• Custom IP: a design that is implemented using custom tools or a combination of place and route and custom tools and delivered as a macro.
• Black box: any module where the internal components cannot be viewed.
• Block: any logical hierarchy that is implemented in a physical design flow and has a single physical boundary. If you change the scope of the tool to a specific block, that block is now the current design.
• Partition: a logical wrapper created around one or more RTL modules used facilitate physical implementation.
• Toplevel: The highest logical hierarchy of a design to be delivered. The amount of PnR at this level should be kept to a minimum unless it is a flat design. This is usually given a codename e.g. crystallake, or follows a sequential naming convention e.g. TPU1
• Top: The highest logical hierarchy of any multi-level block. e.g. pcie_top
• Cell: liberty timing format provides the “cell” definition, which would complement the physical information defined by “macro” in the LEF. Also is used in place of instances in some tools (e.g. get_cells).
• Libcell: short for library cells, specifically, the timing information of a macro or stdcell. Also provides other attributes not described by the LEF such as cell type.
• Standard cell (stdcell): a special type of macro that is intended to be placed on a placement site by an auto place and route tool.

Notes:

• All stdcells are macros, not all macros are stdcells.
• All macros are black boxes. Not all black boxes are macros.
• All partitions are blocks, not all blocks are partitions.
• A module can be converted to a block, a block can be converted to a black box, and a black box can be converted to a macro.
• Due to the very different usage of the word “cell” between EDA vendors, it should be avoided by itself. Library cell, physical cell, reference cell, standard cell, are preferred.