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Silicon Design

Efficiency through Automation

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Make it faster.

Getting complex systems into a single step.

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Let's Work Together!

Consulting

Avoid common pitfalls and wasting thousands of hours by partnering with JDWK consulting

Design

SoC design process focuses on full-chip implementation and verification

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Training

Upskill or reskill your workforce with hands-on corporate team training

Experience

Our engineers have worked on chips ranging from 90nm to 3nm

Highest Quality

SoC design process focuses on full-chip implementation

Reductionism & Syntheticism

We are standardizing flows and IP to make it faster to tape out

Blog

Centralized vs Localized Flows
Centralized vs Localized Flows

The argument for centralized flows is that it is difficult to debug failures and unexpected results if you don’t know wha...

IP Terminology (definitions for VLSI)
IP Terminology (definitions for VLSI)

There is often confusion in the industry about what exactly these words mean as they are often used interchangeably and can cha...

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